The present invention relates generally to integrated circuit (IC) device testing techniques and, more particularly, to a method for testing hold path faults using functional clocking.
A hold fault occurs when there is a delay on the clock path to a capture memory element, and an intermediate memory element launches a transition twice in the time that the capture memory element captures only once. This causes data to move two levels of logic in one clock cycle or at one clock edge. A hold path fault occurs when a logic transition travels from a launch memory element down a short data path to a capture memory element faster than the clock signal can reach the capture memory element. The entire datapath is the fault site, as opposed to a transition fault, which is situated at a single node in a circuit.
The classical path fault model, based on launching a transition at a launch memory element, moving the transition robustly down the path-under-test, and capturing the transition at a capture memory element, can be used to test setup path faults on data paths in logic. However, test generation using the classical path fault model inherently favors setup tests on data paths. Hold path faults on short data paths are tested only serendipitously. Testing of hold path faults on short data paths is not guaranteed using classical path test generation algorithms, which incorporate two clock pulses to launch and capture a test pattern. In particular, the second clock pulse may overwrite the faulty value caused by a hold path fault, thus masking such a fault. Accordingly, hold path testing is a difficult problem.
At-speed structural test (ASST) tests setup delay faults on long paths (data path faults) well in logic. However, test generation inherently favors setup tests on long paths. Hold path faults on short paths are tested serendipitously. Testing of hold path faults on short paths is not guaranteed. Testing hold path faults on short paths requires only one clock pulse. ASST uses two pulses and the second pulse may overwrite the faulty value due to a hold path fault, such that the hold path fault is masked.